Wafer Level Chip Size Packaging (WLCSP) is a technology in which a whole wafer is packaged and tested first, and then diced into individual chips. The size of a chip after being packaged is almost the same as that of a bare chip. Such a technology is totally different from conventional packaging technologies such as Ceramic Leadless Chip Carrier and Organic Leadless Chip Carrier, and satisfies the market's requirements for micro-electronic products, e.g., light in weight, small in size, thin in thickness and low in cost. Packaging with the WLCSP technology realizes high miniaturization, and the chip cost decreases significantly with the decrease of the chip size and the increase of the wafer size. The WLCSP technology, which, when being implemented, may take into account the IC design, wafer fabrication and packaging test in combination, is currently a hot point in the packaging field and becomes one of the development trends of the packaging technologies.
Chinese patent application No. 200610096807.5 discloses a method of wafer level chip size packaging, which mainly includes the following steps.
Referring to FIG. 1, bonding a semiconductor wafer 1 with a first glass substrate 2 having a same size as that of the semiconductor wafer 1. As such, devices formed on the wafer can be protected by the first glass substrate from environmental pollution and damage at initial packaging stage.
Referring to FIG. 2, thinning a back surface of the semiconductor wafer 1 which is opposite to the first glass substrate 2, and performing selectively etching on the back surface using photolithography and plasma etching processes, to form a first plurality of V-shaped grooves as dicing streets and to expose some of pads 11 (namely, chip electrodes).
Referring to FIG. 3, filling an insulating dielectric material into the first V-shaped grooves, and bonding a second glass substrate 3 and a solder mask 4 on the back surface of the semiconductor wafer 1. The second glass substrate 3 serves to support the semiconductor wafer 1, while the electric and heat insulation material of the solder mask 4 functions as a mechanical buffer to protect the semiconductor wafer 1 during subsequent mechanical cutting processes.
Referring to FIG. 4, half-cutting (not cutting through and separating the chip) where the first V-shaped grooves locates, to form a second plurality of V-shaped grooves as dicing streets, and to expose the pads 11 from sides of the second V-shaped grooves.
Referring to FIG. 5, forming an out wire 12 using an electroplating process, where one end of the out wire 12 is connected to a pad 11 in the second V-shaped grooves, and another end of the out wire 12 extends to the back surface of the wafer. Therefore, the electric function of the pad 11 may extend to the back surface of the wafer through the out wire 12.
Referring to FIG. 6, selectively forming an insulating protective layer 14, exposing a portion of the out wire 12, and form a soldered bump 15 on the exposed out wire 12. The wafer is then cut along the second V-shaped grooves to form a plurality of individual chips, which are then packaged. In this way, the total packaging process is finished.
However, the conventional method of wafer level chip size packaging has following disadvantages. During forming an out wire 12 using an electroplating process, metals in the dicing streets (the second V-shaped grooves as described above) are likely to detach from it, which may short out circuits. In addition, after being cut, the side of the individual chips, namely the side wall of the second V-shaped grooves, is exposed to external environments, which is likely to be damaged during outer skin packaging, which may break the out wire and further affect the chip's yield.